As is well known, CMOS processes are widely used to manufacture devices for analog applications, in view of the low power consumption and high integration density features of MOS devices compared to bipolar transistors.
A prerequisite is, however, that the basic CMOS process be modified by the addition of new options, namely:
high linearity capacitors (approximately 50 ppm/V, with a specific capacitance of 0.5 to 1 pF/.mu.m.sup.2); PA1 high specific value precision resistors (approximately 1 to 2 kohm/square); and PA1 low threshold MOS transistors (below 0.8 V). PA1 V.sub.FB is the flat band voltage, PA1 .PHI..sub.S is the surface potential of the substrate, PA1 K.sub.s is the silicon dielectric constant, PA1 .epsilon.o is the vacuum dielectric constant, PA1 q is the electron charge, PA1 N is the concentration of dopant in the region which is to accommodate the transistor, and PA1 Co is the capacity per square of the gate dielectric surface. PA1 .PHI..sub.MS =the difference between the gate electrode work function and the silicon substrate work function, PA1 Q.sub.F =fixed charge of the gate dielectric, and PA1 C.sub.O =capacitance of the gate dielectric.
High linearity capacitors are either formed between two layers of polycrystalline silicon or between a layer of polycrystalline silicon and a diffusion. To provide the required linearity values, they require very heavy doping of both electrodes.
Precision resistors are formed in a lightly doped layer of slightly doped polycrystalline silicon, which is normally obtained, protecting the gate polysilicon from the N+ doping through an appropriate oxide mask.
As to MOS transistors having polysilicon gate terminals, it is fairly difficult to obtain low threshold voltages and small gaps between the source and drain active regions, at one time and in both transistors of the CMOS pair.
Both these features are attractive in any transistor type, because they allow low supply voltages to be used while still affording high speed of response and high integration densities.
Analog applications specifically require that transistors with low threshold voltages be used, both for improved linearity of response and on account of the present trend toward lower power requirements. To fully appreciate the aspects of this invention, mention should be made of the expedients that may be used to produce low threshold voltage transistors.
A first reference is the work by A. S. Grove, "Physics and Technology of Semiconductor Devices", published by Wiley, where the threshold voltage of an MOS transistor is expressed as a function of characteristic parameters: ##EQU1## where: V.sub.T is the threshold,
In this relation, the sign (-) denotes P-channel transistors and the sign (+) N-channel transistors. Accordingly, the threshold voltage will be negative for the P-channel transistors and positive for N-channel ones.
The value of the threshold voltage depends on the three terms which appear in the right-hand part of the relation (1).
In the N-channel transistors of conventional CMOS devices, two terms have opposite signs, namely V.sub.FB is negative whereas .PHI..sub.s is positive, and they cancel each other almost completely.
It follows that the threshold voltage will solely be dependent on the third term, which can lead to V.sub.T taking the desired value by variation.
For instance, in standard CMOS processes wherein the gate terminal of an N-channel transistor is formed by a polycrystalline layer doped with phosphorus, fairly low threshold voltages of about 0.3 to 0.5 Volts can be obtained.
In the instance of the P-channel transistors of CMOS devices, on the other hand, both terms V.sub.FB and .PHI..sub.s are negative and the third term, which is positive, is preceded by the minus sign. Therefore, all these terms will make a non-negligible contribution to the value of the threshold voltage. In any event, the value of V.sub.T will never drop below the modulo of the sum of the first two terms.
In general, threshold voltages on the order of -1.5 to -1.7 Volts can be obtained for P-channel MOS transistors.
The threshold voltages thus obtained are inadequate for normal applications, whether digital or analog. Therefore, the thresholds of N-channel transistors should be raised and those of P-channel transistors lowered. This can be accomplished by manipulating the third term of equation (1) in order to alter the surface concentration of N-dopant. Thus, the threshold of N-channel transistors must be raised, and this is accomplished by an additional implantation of boron just beneath the gate oxide.
With P-channel transistors, on the contrary, the dopant concentration must be reduced, and this is accomplished by an appropriate implantation of boron compensating the substrate N-doping. However, some problems are encountered in so doing.
In fact, when the concentration of N-dopant is greatly reduced in the substrate of P-channel transistors, under certain bias conditions a deep conductive channel may be formed at gate voltages below the threshold voltage (a phenomenon called "punch-through"). It therefore becomes impossible to control the transistor.
This problem may be avoided by increasing the gap between the source and drain regions of the P-channel transistor.
In this way, however, the transistor length is increased, which results in decreased integration density and speed of response.
Furthermore, in the instance of enhanced reduction of the threshold voltage and formation of the deep channel, even an increase of the channel length may prove ineffective to control the transistor current loss, in spite of the gate being grounded.
To lower the threshold voltage of P-channel transistors one might act on the flat band voltage V.sub.FB. As previously mentioned, this voltage is a negative one, but to significantly lower the threshold V.sub.T it would have been convenient if such band voltage was positive.
As the skilled person in the art knows well, the flat band voltage is substantially related to the difference between the Fermi energy of the substrate which is to accommodate the transistor and the Fermi energy of the gate electrode. Further, the flat band voltage is expressed in the following relation: EQU V.sub.FB =.PHI..sub.MS -Q.sub.F/C.sbsb.o ( 2)
where:
In a P-channel transistor, the substrate is an N type, which means that its Fermi level is shifted toward the conduction band, e.g. toward high energy levels. Where a transistor of that kind is incorporated in a CMOS device with polysilicon gate terminals, the layer of polycrystalline silicon is usually an N+ type, which means that its Fermi energy lies even closer to the conduction band than that of the substrate.
Accordingly, the Fermi energy of the substrate is lower than that of the gate electrode and the flat band voltage will take a negative value of about -250 mV.
To make this value a positive one, e.g. of about 750 mV, it is necessary to shift the Fermi energy of the gate electrode toward the valency band, that is toward energy levels lower than those of the substrate. This involves heavy doping of the polycrystalline silicon with impurities of the P+ type.
When a positive flat band voltage is used in a P-channel transistor, a sufficiently low threshold voltage can be obtained even if a fairly high proportion of the dopant is left over in the substrate. Thus, such an approach would yield a P-channel transistor having a low threshold voltage and a small gap between the active regions.